Source/drain junction extension plays an important role in controlling the short channel effect of MOS devices and improving the device driving capability.
Source/drain junction extension is directly adjacent to the channel conductive region. As the gate length decreases continuously, the junction depth of the source/drain junction extension is required to be lower so as to curb the increasingly serious short-channel channel effect. However, decrease in the junction depth of the source/drain junction extension leads to a larger resistance. If the series resistance of the source/drain junction extension is not reduced timely, the parasitic resistance of the source/drain junction extension will play a dominant role in the device on-resistance, and thus affect or diminish the advantage of various strained channel technologies to improve the mobility and lower equivalent channel resistance.
In the prior art, methods such as ultra-low-energy implantation (for example, the implantation energy less than 1 keV) and high-energy transient laser annealing are usually employed to reduce the junction depth of the source/drain junction extension and to enhance the activation concentration to reduce resistance. However, with the scale-down of IC technology nodes, the requirements of the device performance for process parameters of the source/drain junction extension become increasingly rigorous, especially for the 22 nm or beyond technology. The difficulties faced by the above technologies are growing.
Therefore, it is desirable to propose a semiconductor structure and a manufacturing method thereof, which allows the semiconductor structure to have a source/drain junction extension with a high doping concentration and a low junction depth.